The magnitude of the real-time digital signal processing challenge attached to large radio astronomical antenna arrays motivates use of high performance computing (HPC) systems. The need for high power efficiency (performance per watt) at remote observatory sites parallels that in HPC broadly, where efficiency is an emerging critical metric. We investigate how the performance per watt of graphics processing units (GPUs) is affected by temperature, core clock frequency and voltage. Our results highlight how the underlying physical processes that govern transistor operation affect power efficiency. In particular, we show experimentally that GPU power consumption grows non-linearly with both temperature and supply voltage, as predicted by physical transistor models. We show lowering GPU supply voltage and increasing clock frequency while maintaining a low die temperature increases the power efficiency of an NVIDIA K20 GPU by up to 37-48% over default settings when running xGPU, a compute-bound code used in radio astronomy. We discuss how temperature-aware power models could be used to reduce power consumption for future HPC installations. Automatic temperature-aware and application-dependent voltage and frequency scaling (T-DVFS and A-DVFS) may provide a mechanism to achieve better power efficiency for a wider range of codes running on GPUs.

A "large-N" correlator that makes use of Field Programmable Gate Arrays and Graphics Processing Units has been deployed as the digital signal processing system for the Long Wavelength Array station at Owens Valley Radio Observatory (LWA-OV), to enable the Large Aperture Experiment to Detect the Dark Ages (LEDA). The system samples a ~100MHz baseband and processes signals from 512 antennas (256 dual polarization) over a ~58MHz instantaneous sub-band, achieving 16.8Tops/s and 0.236 Tbit/s throughput in a 9kW envelope and single rack footprint. The output data rate is 260MB/s for 9 second time averaging of cross-power and 1 second averaging of total-power data. At deployment, the LWA-OV correlator was the largest in production in terms of N and is the third largest in terms of complex multiply accumulations, after the Very Large Array and Atacama Large Millimeter Array. The correlator's comparatively fast development time and low cost establish a practical foundation for the scalability of a modular, heterogeneous, computing architecture.

We present a Stokes I, Q and U survey at 189 MHz with the Murchison Widefield Array 32 element prototype covering 2400 deg². The survey has a 15.6 arcmin angular resolution and achieves a noise level of 15 mJy beam^–1. We demonstrate a novel interferometric data analysis that involves calibration of drift scan data, integration through the co-addition of warped snapshot images, and deconvolution of the point-spread function through forward modeling. We present a point source catalog down to a flux limit of 4 Jy. We detect polarization from only one of the sources, PMN J0351-2744, at a level of 1.8% ± 0.4%, whereas the remaining sources have a polarization fraction below 2%. Compared to a reported average value of 7% at 1.4 GHz, the polarization fraction of compact sources significantly decreases at low frequencies. We find a wealth of diffuse polarized emission across a large area of the survey with a maximum peak of ~13 K, primarily with positive rotation measure values smaller than +10 rad m^–2. The small values observed indicate that the emission is likely to have a local origin (closer than a few hundred parsecs). There is a large sky area at α ≥ 2^h30^m where the diffuse polarized emission rms is fainter than 1 K. Within this area of low Galactic polarization we characterize the foreground properties in a cold sky patch at (α, δ) = (4^h, –276) in terms of three-dimensional power spectra.

We present a highly parallel implementation of the cross-correlation of time-series data using graphics processing units (GPUs), which is scalable to hundreds of independent inputs and suitable for the processing of signals from ‘large-’ arrays of many radio antennas. The computational part of the algorithm, the X-engine, is implemented efficiently on NVIDIA’s Fermi architecture, sustaining up to 79% of the peak single-precision floating-point throughput. We compare performance obtained for hardware- and software-managed caches, observing significantly better performance for the latter. The high performance reported involves use of a multi-level data tiling strategy in memory and use of a pipelined algorithm with simultaneous computation and transfer of data from host to device memory. The speed of code development, flexibility, and low cost of the GPU implementations compared with application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) implementations have the potential to greatly shorten the cycle of correlator development and deployment, for cases where some power-consumption penalty can be tolerated.