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A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation

Citation:

Yildiz Sinangil, Sabrina M. Neuman, Mahmut E Sinangil, Nathan Ickes, George Bezerra, Eric Lau, Jason E Miller, Henry C Hoffmann, Srini Devadas, and Anantha P Chandraksan. 2014. “A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation.” In 2014 Symposium on VLSI Circuits Digest of Technical Papers (VLSI Circuits), Pp. 1–2. IEEE. Full Text
A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation

Abstract:

This paper presents a self-aware processor with energy monitoring circuits that can measure actual energy consumption of the key blocks. The monitors are embedded into on-chip DC/DC converters and generate results within 10% of accuracy with minimal power (<0.1%) and area (<1%) overhead. Our system, which is implemented in 0.18um technology, is designed to be voltage scalable from 1.8V down to 0.6V. Low-voltage SRAM operation is made possible through the use of 8T bit-cells and write-assists. The d-caches are designed to be re-configurable in associativity and size to adapt to compute- versus cache-bound phases of applications. Cache configuration is performed in < 3 clock cycles including tag invalidation. These hardware features enable a software self-aware computation engine (SEEC) to dynamically adapt the processor to meet performance and energy goals. Measurement results show that up to 8.4x energy savings can be achieved with DVFS and self-adaptation.
See also: Power-Aware Computing
Last updated on 10/06/2022